1. Field of the Invention
The present invention relates to circuit design, and particularly to a timing verification method for deterministic and stochastic networks and circuits that provides a computerized method that includes a non-enumerative path length analysis algorithm for deterministic and stochastic directed acyclic graphs (DAGs) with applications to timing verification of circuits.
2. Description of the Related Art
A combinational logic circuit can be represented as a timing graph that describes the logic gates in the circuit with the directional connections between different gates. Program evaluation and review technique (PERT) is popularly used in static timing analysis, it is also known as the CPM (critical path method), which is the most widely used technique, used for delay calculations. CPM can be used to calculate the worst-case delay of a combinational circuit. Critical paths, required times and slacks are also a number of timing parameters for a combinational circuit that can also be calculated. Incremental timing analysis can be used to speed up the delay calculation. A negative aspect of the CPM is that of false paths, which results because the CPM completely ignores the Boolean relationships in a circuit, and works with purely topological properties. This renders the critical path delay found using CPM as pessimistic in the most general cases.
Thus, a timing verification method for deterministic and stochastic networks and circuits solving the aforementioned problems is desired.